2068 Project
1 message · 2004-07-01 → 2004-07-01 · Yahoo Group era · View archive on archive.org
Participants: Jeff
Preserved from the Timex/Sinclair 2068 Yahoo Group (2001–2019), which is no longer online. Text reproduced from the archive.org archive; email addresses masked.
Messages
1. 2068 Project
Jeff · Thu, 01 Jul 2004 16:01
Alvin;
I certainly understand your time crunch for hobbies.
I hadn't thought of dynamically asserting /BE because I was
concerned about overall system timing issues.
My original thought was a 512k RAM/ 512k flash interface that
used /ROSCS for accessing the memories. The 8K chunks would be
mapped in using a register file that would decode and translate
A[15..13] to an 8 bit address extension on-the-fly to map the 8K
windows anywhere in the 1M space and even allow different addresses
to alias to the same physical memory. Ideally, the main and
extension ROMs would be copied into the flash to allow bug fixes and
updating the firmware.
An RTC and IDE interface would be available and I was thinking of
adding a USB 1.1 host interface. This would require writing a bunch
of drivers, but it might be somewhat fun.
It wouldn't be difficult to add a second dock bank connector and
enable (/ROSCS_XTERN) to allow reading cartidges.
I haven't decided on a PC link yet, but the SMSC LAN91C96 ethernet
controller looks interesting :).
I figure all of the support logic could fit into a Xilix 95144
100PQFP (most of it fits into an Altera 7128 PLCC84). Anything
fancier would require an FPGA.
The Z88DK small C compiler could be modified for far memory to use
this hardware.
If you're gonna dream, dream big!