Expansion Interface
3 messages · 2004-07-23 → 2004-08-25 · Yahoo Group era · View archive on archive.org
Participants: Jeff, Jack Boatwright
Preserved from the Timex/Sinclair 2068 Yahoo Group (2001–2019), which is no longer online. Text reproduced from the archive.org archive; email addresses masked.
Messages
1. Expansion Interface
Jeff · Fri, 23 Jul 2004 20:34
All;
I'd like some input as to what you all would consider the basic
minimal TS2068 expansion interface.
My suggestion is:
1. 512K RAM
2. 512K flash
3. IDE hard disk interface
4. Real time clock
5. RS232 compatible interface
6. Some sort of expansion bus
Optional goodies (connected to expansion bus)
1. 10 baseT ethernet
2. USB 1.1
3. VGA display
4. Audio output card (this could have LOTS of flash storage on board)
2. Re: [ts2068] Expansion Interface
Jack Boatwright · Tue, 3 Aug 2004 19:22:
Yes!
:-O
Also, I have measured the "box" internally. The expansion board
(with daughterboards) can be no more than 2 inches tall or it will
not fit. This is the maximum space from the bottom to the top,
internally. I envision some space needed for the 'mounting
apparatus', too.
Jack
----- Original Message -----
From: "Jeff" <[email]>
To: <[email]>
Sent: Friday, July 23, 2004 1:34 PM
Subject: [ts2068] Expansion Interface
> All;
> I'd like some input as to what you all would consider the
basic
> minimal TS2068 expansion interface.
>
> My suggestion is:
> 1. 512K RAM
> 2. 512K flash
> 3. IDE hard disk interface
> 4. Real time clock
> 5. RS232 compatible interface
> 6. Some sort of expansion bus
>
> Optional goodies (connected to expansion bus)
> 1. 10 baseT ethernet
> 2. USB 1.1
> 3. VGA display
> 4. Audio output card (this could have LOTS of flash storage on
board)
>
>
>
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3. Expansion Interface
Jeff · Wed, 25 Aug 2004 02:11
All;
I have completed what I think is the final architectural definition
for the interface. The file name is 2068_Interface_A.ZIP. As
before, these are PDF files. I expect a few more iterations before a
PCB is made but barring major issues this is the final version.
There have been some major changes between the preliminary design and
this one as follows:
1. The USB controller has been removed. I decided that if this is
desired it can be included on an expansion card. There was just not
enough space on the PCB and it would have added cost for a feature
most people may not want, need, or use.
2. An AC'97 codec port was added. I decided not to put the codec on
this board because it would take up a LOT of area. You'd be suprised
at just how many components (and room) the support circuitry for the
audio chip takes. This will also inhabit a daughter board. I have a
preliminary design that is available to anyone who wants to see it.
This will be the first daughter board produced (even before the USB
adapter) because I think it would relly cool.
3. Memory has been changed from SRAM to DRAM in 30 pin SIMM
modules. There are two sockets that will accept 1MB, 4MB, and 16MB
modules in any combination. Even though the DRAMs are slower than
the SRAMs they should still be fast enough for a 4MHz Z80 system and
the FPGA's peripheral controllers.
4. One standard 16 bit IDE port.
5. One expansion bus. I haven't decided whether to include a YABUS
connector. Let me know if this is desired.
6. One IBM compatible parallel printer port and two serial ports.
This uses the TL16C552AFN UART chip.
7. A port for a ZWorld RCM3700 module for ethernet and
coprocessing. This is simply designer's perrogative.
8. FPGA is a Xilinx Spartan II. These come in 30K, 50K, 100K, 150K,
and 200K gate sizes. I'll probably put the 200K devices on the first
protos because the incremental cost is relatively low and lots 'o
logic is a good thing for a prototype.
9. FPGA configuration uses a PIC16F872 microcontroller. I decided
on this rather than a state machine because of its flexibility.
Other reasons are:
a. allows use of a much cheaper configuration storage device
(AT45DB041B-SC-2.5).
b. allows updating the FPGA using a standard serial port and PC
c. allows updating the boot flash the same way
I have not included a way to update the FPGA configurator from the
2068 because everyone who is in this group already has a PC and
internet access so I didn't think it was vital for the 2068 to have
this capability.
Secondly, all of the early work will be development and I wanted an
interface that was reasonably smart to allow memory dumps etc.
I will be finalizing the bill of materials for the basic board and
will have a projected cost soon.