Highspeed Bus Expansion
1 message · 2004-07-06 → 2004-07-06 · Yahoo Group era · View archive on archive.org
Participants: Jeff
Preserved from the Timex/Sinclair 2068 Yahoo Group (2001–2019), which is no longer online. Text reproduced from the archive.org archive; email addresses masked.
Messages
1. Highspeed Bus Expansion
Jeff · Tue, 06 Jul 2004 19:12
Alvin;
One way to do this would be to use a bus interface unit in an FPGA
to turn the expansion RAM into a psuedo-dual port memory. One can
certainly get memory fast enough - 20ns 512k SRAMs are available and
are not too expensive. If the DMA controller ran at 20+MHz it could
monitor the Z80 bus and do a high speed read or write to an on-chip
Z80 bus interface that would match the internal memory interface to
the Z80 bus. If the context switch happened quickly enough, the Z80
wouldn't even know it was sharing memory and would not need any wait
states. This method would lend itself to any of the forementioned
memory expansion schemes.
One of the big problems with the 2068 architecture is that writes
to video RAM can be very slow. If the TM is correct, when the SCLD
detects the Z80 attempting to access the video ram while the video
controller is active, it suspends the CPU until the next vertical
retrace period. I bring this up because while we can speed up most
aspects of the machine, anything that requires reading/updating the
screen will memory hit this bottleneck head on (unless we implement a
vertical retrace interrupt or (grin) a VGA interface...)