Interface Schematics
3 messages · 2004-07-18 → 2004-07-19 · Yahoo Group era · View archive on archive.org
Participants: Jeff, Jack Boatwright, Jeff Burrell
Preserved from the Timex/Sinclair 2068 Yahoo Group (2001–2019), which is no longer online. Text reproduced from the archive.org archive; email addresses masked.
Messages
1. Interface Schematics
Jeff · Sun, 18 Jul 2004 02:17
All;
I've posted the first cut at schematics for the proposed
interface. They are in the files area as 2068_INTERFACE.ZIP. The
zip file contains PDFs of the schematic sheets and a brief readme
file.
I am aware that the schematics need more massaging and clean-up
work and that layout WILL change the pin assignments to the FPGA.
Also some of the dedicated input pins are not yet pulled up and I
haven't put the 32MHz oscillator on the board yet. I wanted to get
something that is close to the final product out for comment. At
least the DRC checker isn't complaining :).
All who are interested in this beast please inspect and comment.
To keep things timely and prevent clutter on this group you can email
me directly at [email]. I have high speed so don't
worry about sending large files. I will be looking at this group as
well so don't be afraid to comment here.
I will be accepting comments for two weeks or until it looks like
the comments/suggestions have petered out, then proceed to the layout
stage.
After I finish the layout I'll post PDFs of the Gerber files for
any more comments.
2. Re: [ts2068] Interface Schematics
Jack Boatwright · Mon, 19 Jul 2004 10:17
Jeff,
I have d/led and printed the files, but have not had a chance to
look at them in depth (not that my limited knowledge will be of
value :). My printer, unfortunately, will only copy in letter
size so the printouts are relatively small (1/4 size +/-).
I assume the size of the pcb to be driven from the finshed layout
of the components.
I am at a stalled point now in the construction of the "box"
(pseudo-BEU). I have come up with the bottom for this, but have
decided not to go much further until what goes inside is designed
and sized (not that I expect this project to be involved in what
I'm up to, but I am dreaming too). ;-) I have decided not to
pursue making this look exactly like the BEU in the Timex photo,
i.e., having beveled edges, etc., as that is merely aestheic and
will only serve to drive production costs up (if it ever gets to
that).
I have earlier stated that the pcb for the box could be as large
as 6" x 15". If there is even a remote possibility that this
project could be housed in the "box" I will wait to see how the
interface to the 2068 is accomplished and how the back of the
"box" would/could be designed for i/o(s) and how a pcb must be
mounted inside. And, of course, the associated cost.
Now to the schematics ....
BTW- there are 2 sheets labeled "13", is one a continuation of the
other?
Jack
----- Original Message -----
From: "Jeff" <[email]>
To: <[email]>
Sent: Saturday, July 17, 2004 7:17 PM
Subject: [ts2068] Interface Schematics
> All;
> I've posted the first cut at schematics for the proposed
> interface. They are in the files area as 2068_INTERFACE.ZIP.
The
> zip file contains PDFs of the schematic sheets and a brief
readme
> file.
>
> I am aware that the schematics need more massaging and
clean-up
> work and that layout WILL change the pin assignments to the
FPGA.
> Also some of the dedicated input pins are not yet pulled up and
I
> haven't put the 32MHz oscillator on the board yet. I wanted to
get
> something that is close to the final product out for comment.
At
> least the DRC checker isn't complaining :).
>
> All who are interested in this beast please inspect and
comment.
> To keep things timely and prevent clutter on this group you can
email
> me directly at [email]. I have high speed so
don't
> worry about sending large files. I will be looking at this
group as
> well so don't be afraid to comment here.
>
> I will be accepting comments for two weeks or until it looks
like
> the comments/suggestions have petered out, then proceed to the
layout
> stage.
>
> After I finish the layout I'll post PDFs of the Gerber files
for
> any more comments.
>
>
>
> Yahoo! Groups Sponsor
> ADVERTISEMENT
>
>
>
>
>
> ----------------------------------------------------------------
----------------
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>
> a.. To visit your group on the web, go to:
> http://groups.yahoo.com/group/ts2068/
>
> b.. To unsubscribe from this group, send an email to:
> [email]
>
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of Service.
>
>
3. Re: [ts2068] Interface Schematics
Jeff Burrell · Mon, 19 Jul 2004 13:14
I would like to use whatever you come up with.
The dual 13's are probably an error on my part. I'll look at the schematics when I get home today.
Jack Boatwright <[email]> wrote:
Jeff,
I have d/led and printed the files, but have not had a chance to
look at them in depth (not that my limited knowledge will be of
value :). My printer, unfortunately, will only copy in letter
size so the printouts are relatively small (1/4 size +/-).
I assume the size of the pcb to be driven from the finshed layout
of the components.
I am at a stalled point now in the construction of the "box"
(pseudo-BEU). I have come up with the bottom for this, but have
decided not to go much further until what goes inside is designed
and sized (not that I expect this project to be involved in what
I'm up to, but I am dreaming too). ;-) I have decided not to
pursue making this look exactly like the BEU in the Timex photo,
i.e., having beveled edges, etc., as that is merely aestheic and
will only serve to drive production costs up (if it ever gets to
that).
I have earlier stated that the pcb for the box could be as large
as 6" x 15". If there is even a remote possibility that this
project could be housed in the "box" I will wait to see how the
interface to the 2068 is accomplished and how the back of the
"box" would/could be designed for i/o(s) and how a pcb must be
mounted inside. And, of course, the associated cost.
Now to the schematics ....
BTW- there are 2 sheets labeled "13", is one a continuation of the
other?
Jack
----- Original Message -----
From: "Jeff" <[email]>
To: <[email]>
Sent: Saturday, July 17, 2004 7:17 PM
Subject: [ts2068] Interface Schematics
> All;
> I've posted the first cut at schematics for the proposed
> interface. They are in the files area as 2068_INTERFACE.ZIP.
The
> zip file contains PDFs of the schematic sheets and a brief
readme
> file.
>
> I am aware that the schematics need more massaging and
clean-up
> work and that layout WILL change the pin assignments to the
FPGA.
> Also some of the dedicated input pins are not yet pulled up and
I
> haven't put the 32MHz oscillator on the board yet. I wanted to
get
> something that is close to the final product out for comment.
At
> least the DRC checker isn't complaining :).
>
> All who are interested in this beast please inspect and
comment.
> To keep things timely and prevent clutter on this group you can
email
> me directly at [email]. I have high speed so
don't
> worry about sending large files. I will be looking at this
group as
> well so don't be afraid to comment here.
>
> I will be accepting comments for two weeks or until it looks
like
> the comments/suggestions have petered out, then proceed to the
layout
> stage.
>
> After I finish the layout I'll post PDFs of the Gerber files
for
> any more comments.
>
>
>
> Yahoo! Groups Sponsor
> ADVERTISEMENT
>
>
>
>
>
> ----------------------------------------------------------------
----------------
> Yahoo! Groups Links
>
> a.. To visit your group on the web, go to:
> http://groups.yahoo.com/group/ts2068/
>
> b.. To unsubscribe from this group, send an email to:
> [email]
>
> c.. Your use of Yahoo! Groups is subject to the Yahoo! Terms
of Service.
>
>
Yahoo! Groups SponsorADVERTISEMENT
---------------------------------
Yahoo! Groups Links
To visit your group on the web, go to:
http://groups.yahoo.com/group/ts2068/
To unsubscribe from this group, send an email to:
[email]
Your use of Yahoo! Groups is subject to the Yahoo! Terms of Service.
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