My idea for memory upgrade
1 message · 2004-07-06 → 2004-07-06 · Yahoo Group era · View archive on archive.org
Participants: Jarek Adamski
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Messages
1. My idea for memory upgrade
Jarek Adamski · Tue, 06 Jul 2004 07:50
Hello,
My work until now evaluated into following scheme:
1. The 64kB is divided into 4 sections (of 16kB each), called
A (#0000..#3FFF), B (#4000..#7FFF), C (#8000..#BFFF) and D
(#C000..#FFFF).
2. Each section can contain one of 256 memory pages.
3. Page for each section is selected with ports #D0..#D3
respectively (addresses taken from Z88).
4. Pages #00..#7F are RAM common to all sections (2MB). I.e.
page #00 can be available 4 times in 64kB adress area. (This
is compatibile to Z88.) Pages #80..#FF can contain different
memory in each section. (This is no more compatibile to Z88.)
5. Pages #80..#FF - in section A is the 2MB ROM. Other
sections have no final definitions. In section B can be the
ROM, but I want to use it to access ISA cards, etc. In
sections C and D it is extra RAM - pages can be common to both
sections (2MB total) or every section can contain own 2MB
(4MB total).
6. The page switcher starts from page #FF in section A
after the reset - this is the system boot page. Page #0F is
system main RAM page (used to hold map of available and used
pages).
7. ZX Spectrum 128kB compatibility. A byte outed to #7FFD
port is written to #D3, but bit 4 is set and bits 3 and 5
are reset (Pentagon 512kB compatibility). Writing to port
#5XFD also resets bit 6 (compatibility with code like:
LD A,#5X: OUT (#FD),A). Pages #15 and #17 have the screen.
I've already designed upgrades for Timex FDD 3000 and Timex
FDD 3 following this scheme (except ZX compatibility). EPROM
is common to A and B sections, upper RAM is common for C and
D.
Now I work to implement this scheme for ZX48, TC2048, TC2068
and TS2068.
I also work on an new bus with 11 extra "memory page" lines,
that will allow to connect eZ80 as card and some other nice
things, like "SPEC256" video card with 8 Z80 CPU and own 1MB
memory for each. Toward the conception "build your own 8 bits
computer". The lines are called B0..B7 (page) and B13, B14,
B15 (converted A13..A15).
As the upgrade to ZX Spectrum 128kB compatibility makes the
port #F4 to work quite messy (as screen pages access the
screen memory via ULA with A14=1, A15=0, despite where in
which section they are currently available, also non-screen
RAM pages generate A15=1), there's a need for duplication
of the circuit beside ULA to work as usual.
My idea for DOCK and EXROM:
1. The #F4 port selects between HOME and DOCK/EXROM (new
circuit, as the one inside ULA no more works correctly).
2. Bit 7 in port #FF selects between DOCK and EXROM (also
duplicated because the ULA internal has no output).
3. The #D4 port selects page for each 8kB section,
respectively #X0D4..#X7D4 for DOCK and #X8D4..#XFD4 for
EXROM. The configuration is done (and available) only at
operating system level - the software is allowed to use only
ports #F4 and #FF.
4. Bits 12 and 13 of port address select the way, the A13
line will be converted. There are four available results:
- no conversion - gives access to #0000..#1FFF of the 16kB
memory bank in even 8kB segments and #2000..#3FFF in odd
segments, so memory from even segments cannot be available
in odd segments,
- inversion - gives access to #2000..#3FFF in even segments
and #0000..#1FFF in odd 8kB segments, still memory from even
segments cannot be available in odd segments,
- always 0 - gives access to #0000..#1FFF of each 16kB memory
bank in every segment (#2000..#3FFF is no more available in
DOCK and EXROM), however a bank can be available in every
segment (like the standard 8kB EXROM 8 times in 64kB),
- always 1 - gives access to #2000..#3FFF of bank in every
segment.
5. Bit 14 of the port address enables external /ROSCS and
/EXROM lines, allowing access to inserted cardridges.
6. Bit 15 can write-protect a segment.
How it works then.
1. Operating system reserves some pages for DOCK and EXROM
(this depends on "emulation mode"). They should no more be
used for HOME, what is marked on #0F page.
2. The series of 16 OUTs to #D4 port sets configuration for
each 8kB segment.
3. Pages configured as ROM should be uploaded with proper
contents (they are still writeable from HOME).
Simulation of an extention can perform a series of OUTs to
#D4 port. Exactly like ZX Spectrum 128kB is simulated with
"hidden" writing contents of #7FFD port into #D3 (bank in
section D) and #D0 (ROM bank) ports.
Jarek Adamski