TS2068 simple upgrade: 512kB RAM, 128kB PEROM
5 messages · 2005-08-12 → 2005-08-14 · Yahoo Group era · View archive on archive.org
Participants: Jarek Adamski, Jeff Burrell
Preserved from the Timex/Sinclair 2068 Yahoo Group (2001–2019), which is no longer online. Text reproduced from the archive.org archive; email addresses masked.
Messages
1. TS2068 simple upgrade: 512kB RAM, 128kB PEROM
Jarek Adamski · Fri, 12 Aug 2005 13:34
Hello!
I try to design a simple internal memory upgrade for
TS2068 and TC2068. I want to use 512kB SRAM, seen in
EXROM/DOCK and 128kB PEROM (29F010), seen in HOME/EXROM.
This is a request for comments.
For the HOME ROM bank switching I've dicided to use
my 4MB switching scheme. So, the responsible port
is #D0.
Bit 7 enables the ROM when set to 1 (0 selects the RAM
bank, not present in this upgrade), except just after
reset (until first write to #D0 port), when the ROM is
forced to seen. Bits 0..2 of #D0 select one of eight
16kB ROM pages seen in HOME. Except the normal bank
selection, the PEROM page can be changed with some extra
conditions regarding bits 5 and 6.
A14 line of PEROM can be controlled with bit 4 in #7FFD
port, when ZX128 compatibility upgrade is installed.
This happens when bit 5 in #D0 is set and gives two ZX
Spectrum 128K ROM banks.
A15 line of PEROM can be controlled with /M1 line, but
only when bit 6 is set. This gives a possibility to
emulate TR-DOS, as it has entry points in area of
character set (#3D00..#3DFF), so switching with /M1
gives other data for normal reading and other for
jumps in that area.
The PEROM is also seen in EXROM. But in this case, A16
line of PEROM is controlled by HOME/EXROM selection (0
for HOME, 1 for EXROM) while A14 and A15 lines are
connected to Z80 ones. So in the EXROM only last 4 pages
are seen (4,5,6,7), as 64kB filling whole bank.
The contents of PEROM pages can be as below; after the
"<->" sign is the extra switching explained
page 0: TS2068 ROM <-> A16 to page 4
page 1: TR-DOS traps <-> /M1 to page 3
page 2: ZXVGS system page
page 3: ROM1 (ZXROM, ZX48) <-> /M1 to page 1
page 4: EXROM (8kB) <-> A16 to page 0 (HOME)
page 5: not assigned
page 6: ROM0 of ZX128 <-> bit 4,#7FFD to page 7
page 7: ROM1 of ZX128 <-> bit 4,#7FFD to page 6
The computer starts from page 0. At this moment, the
standard 2068 ROM is used. It can be modified slightly
to display "boot menu", using remaining 8kB of the page
4 (the EXROM one). Value written to #D0 port should be
#80.
When you select ZXVGS mode, the pages used are 1, 2 and
3. Page 3 (#C1 or #C3 is written to #D0 port, bit 1 has
no matter) works as ZX Spectrum 48kB ROM, but opcodes are
taken from page 1 (/M1=0). Page 2 (#82 written to #D0
port) is selected when ZXVGS functions are called. ZXVGS
is operating system, that can control mass storage devices
like FDD, HDD and file server connected with cable.
Also, ZX Spectrum 128kB mode can be set. In this mode,
pages 6 and 7 are used. (#A6 or #A7 is written to #D0
port, the bit 0 has no matter.)
Alternatively, pages 4, 5, 6 and 7 can be used as 64kB
ROM in EXROM bank. In this case the ZX Spectrum 128kB
configuration must be removed or replace the ZXVGS one.
Separate problem is the 512kB SRAM. I want it to be seen
in EXROM and optionally in DOCK. My assumptions are that
the RAM should:
- be compatibile to ZXVGS UPB upgrade (32kB RAM in lower
32kB of EXROM) - beside ZXVGS, this configuration can be
used by CPM22QED UPB (CP/M) without extra cartridges,
- offer 32kB RAM in upper 32kB of EXROM, what is intended
to work in 2068 ROM mode,
- be compatibile to Larken ramdisk (8 pages of 32kB, in
upper 32kB of DOCK, switched with bits 0..2 of #07 port),
- coexist with Larken ramdisk cartridge located in DOCK,
- have higher priority in EXROM than above PEROM.
Any suggestions are welcome.
2. Re: [ts2068] TS2068 simple upgrade: 512kB RAM, 128kB PEROM
Jeff Burrell · Fri, 12 Aug 2005 18:10
Jerek;
I've been side-tracked by my work on the TS2068 core for the C-1 Reconfigurable computer.
I've looked at (and prototyped a version) a similar type of a memory expansion for the 2068. I used an Altera 70128 CPLD to provide a flexible memory mapping scheme for 512K of RAM and 512K of flash (29C040). I used ports $00-07 to load a register file that allowed any chunk in the dock bank to be mapped into any 8K block of the expansion memory. I can provide you with a schematic or the AHDL code for the interface if you want it. If you use the surface mount packages for the CPLD and memories, you can make a very small package that might fit into the 2068 case.
I would recommend usint the 29C devices since you can rewrite 512 byte pages instead of requiring you to erase and rewrite the whole chip. You can also software lock the devices to prevent inadvertent reprogramming them.
Jarek Adamski <[email]> wrote:
Hello!
I try to design a simple internal memory upgrade for
TS2068 and TC2068. I want to use 512kB SRAM, seen in
EXROM/DOCK and 128kB PEROM (29F010), seen in HOME/EXROM.
This is a request for comments.
For the HOME ROM bank switching I've dicided to use
my 4MB switching scheme. So, the responsible port
is #D0.
Bit 7 enables the ROM when set to 1 (0 selects the RAM
bank, not present in this upgrade), except just after
reset (until first write to #D0 port), when the ROM is
forced to seen. Bits 0..2 of #D0 select one of eight
16kB ROM pages seen in HOME. Except the normal bank
selection, the PEROM page can be changed with some extra
conditions regarding bits 5 and 6.
A14 line of PEROM can be controlled with bit 4 in #7FFD
port, when ZX128 compatibility upgrade is installed.
This happens when bit 5 in #D0 is set and gives two ZX
Spectrum 128K ROM banks.
A15 line of PEROM can be controlled with /M1 line, but
only when bit 6 is set. This gives a possibility to
emulate TR-DOS, as it has entry points in area of
character set (#3D00..#3DFF), so switching with /M1
gives other data for normal reading and other for
jumps in that area.
The PEROM is also seen in EXROM. But in this case, A16
line of PEROM is controlled by HOME/EXROM selection (0
for HOME, 1 for EXROM) while A14 and A15 lines are
connected to Z80 ones. So in the EXROM only last 4 pages
are seen (4,5,6,7), as 64kB filling whole bank.
The contents of PEROM pages can be as below; after the
"<->" sign is the extra switching explained
page 0: TS2068 ROM <-> A16 to page 4
page 1: TR-DOS traps <-> /M1 to page 3
page 2: ZXVGS system page
page 3: ROM1 (ZXROM, ZX48) <-> /M1 to page 1
page 4: EXROM (8kB) <-> A16 to page 0 (HOME)
page 5: not assigned
page 6: ROM0 of ZX128 <-> bit 4,#7FFD to page 7
page 7: ROM1 of ZX128 <-> bit 4,#7FFD to page 6
The computer starts from page 0. At this moment, the
standard 2068 ROM is used. It can be modified slightly
to display "boot menu", using remaining 8kB of the page
4 (the EXROM one). Value written to #D0 port should be
#80.
When you select ZXVGS mode, the pages used are 1, 2 and
3. Page 3 (#C1 or #C3 is written to #D0 port, bit 1 has
no matter) works as ZX Spectrum 48kB ROM, but opcodes are
taken from page 1 (/M1=0). Page 2 (#82 written to #D0
port) is selected when ZXVGS functions are called. ZXVGS
is operating system, that can control mass storage devices
like FDD, HDD and file server connected with cable.
Also, ZX Spectrum 128kB mode can be set. In this mode,
pages 6 and 7 are used. (#A6 or #A7 is written to #D0
port, the bit 0 has no matter.)
Alternatively, pages 4, 5, 6 and 7 can be used as 64kB
ROM in EXROM bank. In this case the ZX Spectrum 128kB
configuration must be removed or replace the ZXVGS one.
Separate problem is the 512kB SRAM. I want it to be seen
in EXROM and optionally in DOCK. My assumptions are that
the RAM should:
- be compatibile to ZXVGS UPB upgrade (32kB RAM in lower
32kB of EXROM) - beside ZXVGS, this configuration can be
used by CPM22QED UPB (CP/M) without extra cartridges,
- offer 32kB RAM in upper 32kB of EXROM, what is intended
to work in 2068 ROM mode,
- be compatibile to Larken ramdisk (8 pages of 32kB, in
upper 32kB of DOCK, switched with bits 0..2 of #07 port),
- coexist with Larken ramdisk cartridge located in DOCK,
- have higher priority in EXROM than above PEROM.
Any suggestions are welcome.
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3. Re: [ts2068] TS2068 simple upgrade: 512kB RAM, 128kB PEROM
Jarek Adamski · Sat, 13 Aug 2005 15:03
Jeff,
I want the upgrade to be simple as possible. I'm not
familiar with programmable logic and I prefer avoid
it, at least in this upgrade.
I've bought 628512 and 29C010 memories in DIL32 cases,
because they are cheap ($6+$3) and I want to use small
boards under them with some 74xx chips in SMD cases,
plus something like 74LS253 for SRAM/PEROM selection.
So, the upgrade cost is $25-$30.
I want the upgrade to be cheap and available both to
Timex Sinclair 2068 and Timex Computer 2068 (their
board layout are different).
The ROM switching is ready and I'm happy with it. But
I still don't know, how to arrange the 512kB SRAM to
get maximal usability.
The upgrade is dedicated mainly for HOME and EXROM,
but option of using 256kB RAM in DOCK is probably most
compatibile to existing software (Larken ramdisk).
What I need to know is - what else it could be
compatibile, beside Larken ramdisk and ZXVGS UPB
upgrade?
I've heard something about 32kB RAM mounted in top
half of EXROM. I wouldn't like to miss a solution
that could be contuinued with my upgrade.
Also, I would like to know, where the SRAM should be
seen just after reset - in DOCK or in EXROM?
Perhaps someone knows, why the Larken ramdisk uses
bit 6 for write-protection and if bits 3, 4, 5, 7 of
port #07 are used for other purposes.
Jarek Adamski
http://8bit.yarek.pl
4. Re: [ts2068] TS2068 simple upgrade: 512kB RAM, 128kB PEROM
Jarek Adamski · Sun, 14 Aug 2005 02:27
Hello!
I have a conception of simple 512kB SRAM switching.
SRAM configurations are limited to 4 possibilities,
in each there are 8 separate pages:
- 64kB DOCK,
- top 32kB DOCK - Larken ramdisk compatibile,
- 64kB EXROM - for ZXVGS UPB compatibility,
- top 32kB EXROM.
When SRAM is mapped to DOCK, has higher priority than
cartridges. SRAM must be mapped to EXROM to access
contents of DOCK cartridges. SRAM mapped to EXROM
has higher priority than PEROM available in EXROM.
The SRAM can have battery backup.
The power-on configuration, due to Larken ramdisk
compatibility can be only the top 32kB DOCK. This
will stop AROS cartridges, but the SRAM can be paged
to EXROM, cardridge contens can be copied to SRAM,
then after reset (or power-on with battery backup)
we get the same effect as using the cardridge.
The SRAM is controlled by two out-only ports. The #0F
one works always and the #07 is available only when
SRAM is mapped to DOCK. The power-on value for the
port is #00, what gives page 0 and write-protection
(Larken ramdisk compatibility).
Because the need for the Larken ramdisk compatibility,
writing values #00..#07 and #40..#47 must select the
top 32kB DOCK configuration. The latch is 6bits wide,
as Larken ramdisk uses 4 bits (0..2 for page selection
and 6 for write-protection) and the memory
configuration selection needs 2 bits more.
Extra bits are:
- bit 7 - when set, moves the SRAM to EXROM and
disables #07 port - so external Larken ramdisk can be
used without memory and port conflict.
- bit 5 - when set, enables the SRAM in bottom 32kB.
These 2 bits are reseted at while power-on, what
forces Larken ramdisk compatibility. However, with
extra logic (inverters) it is possible to get another
power-on configuration. The question is: is there a
need?
As mentioned before, the latch is 6bit - something
like 74LS174. The port address decoder can be build
of 74LS138, with help of diodes and resistors to
allow A7, A6, A5, A4, A3, /IORQ and /WR to be
decoded and transistor to switch the port #07
auvailability (when bit 7 in latch is set, the #07
port is bloked). The final chip is 74LS151
multiplexer, where bits 5 and 7 of latch and A15
of Z80 select the /ROSCS or /EXROM that enables
the SRAM. /MREQ is provided with diode or trasistor.
All above elements should fit on small board placed
under SRAM chip (74LS151 as DIL, other as SMD).
74LS151 configuration:
bit
7 5 A15 Y
- - --- -
0 0 0 1 - not in bottom 32kB
0 0 1 /ROSCS - top 32kB DOCK
0 1 0 /ROSCS - 64kB DOCK
0 1 1 /ROSCS - 64kB DOCK
1 0 0 1 - not in bottom 32kB
1 0 1 /EXROM - top 32kB EXROM
1 1 0 /EXROM - 64kB EXROM
1 1 1 /EXROM - 64kB EXROM
When Y output enables SRAM (low state), the /Y
output locks PEROM and /ROSCS line available
in cartridge and edge slots. Also /EXROM line
on these slots could be locked, but this has
limited sense, since extra EXROM memory
connected to unmodified TS2068 would cause
conflicts.
The upgrade doesn't stop the possibility of
installing 4MB RAM in HOME bank.
--
Jarek Adamski
http://8bit.yarek.pl
5. Re: [ts2068] TS2068 simple upgrade: 512kB RAM, 128kB PEROM
Jeff Burrell · Sun, 14 Aug 2005 12:17
Jarek;
I understand your reluctance to use programmable logic, but it isn't too hard to do. I wrote a design in Altera's AHDL today (Sunday) for a memory mapper that uses an Altera 3128 100 pin CPLD. It would need a 3.3V regulator for the core but an LDO is inexpensive and easy to add to a PCB. The CPLD pins accept 5V inputs and output 3.3V - well above the TTL minimum. The cost of the device is $8.60 on Digikey's web site so it's probably not much more than TTL chips. The CPLD can also make PCB routing much easier since much of the routing that would be needed on the PCB can be pushed into the CPLD and the CPLD pin out can be optimized for PCB layout. It is not unusual for me to change the CPLD pin assignments several times as the PCB layout progresses. I have put these devices on a 2-sided PCB where I work, so that should not be a problem.
If you want to use a CPLD, I would be very willing to donate the logic design with whatever releases you need.
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